Next-Generation Arithmetic: A Revolution for AI, HPC, and Data Science

Many people are surprised by the idea that the way we represent numbers on computers is in dire need of improvement, having assumed that the issue was decided decades ago. Now that Moore's law is no longer providing gains by shrinking transistor sizes, the path forward is to find number representations that maximize information per bit. The 2016 invention of posit arithmetic is leading to better answers with fewer bits compared to the IEEE Standard floating-point format, which is actually an Intel proprietary format designed in 1976 for the first IBM PC. This talk presents the design goals for a new number format and how the next-generation arithmetic is providing energy efficiency gains of 4× and greater, similar to two turns of Moore's law.

Bio
John Gustafson serves on several Boards and is Chief Scientist at Vq Research. He is also a Visiting Scholar at ASU, after having been a Professor at National University of Singapore for six years.

Gustafson was Senior Fellow and Chief Product Architect at AMD until June 2013. He left to complete a book on a revolutionary new approach to computer arithmetic, "The End of Error: Unum Computing," released in 2015. A sequel is now out, "Every Bit Counts: Posit Computing" with all new material. He has joined the Boards of SSRLabs, Etaphase Inc., and Clustered Systems Company Inc. He co-founded Vq Research, a company pursuing a new approach to the creation of MLCCs with very high energy density. John was a Director at Intel Labs from March 2009 to February 2012; he managed the group charged with driving off-roadmap, high-impact exploratory research.

He was a member of the Board of Directors of Massively Parallel Technologies (MPT) from 2007 to May 2014, a company where he took the CEO role from May, 2008 to March 2009. MPT is a parallel computing company founded in 1999 that received multiple contracts from the DARPA HPCS program (the same one that funded Cray, Sun, and IBM); it is now applying the patented IP it generated during that phase to the creation of firmware/hardware product lines that allow HPC clusters to scale to thousands of processors on a single problem. Its communication technology is complementary to the arithmetic accelerators made by companies like ClearSpeed.

Gustafson joined ClearSpeed in 2005 as CTO for HPC after leading HPC efforts at Sun. He has 42 years experience using and designing compute-intensive systems. His pioneering work on a 1024-processor nCUBE at Sandia created a watershed in parallel computing, for which he received the inaugural Gordon Bell Award. He has received three R&D 100 Awards for innovative performance models, including the model commonly known as Gustafson's Law or Scaled Speedup.

He received his B.S. degree from Caltech and his M.S. and Ph.D. degrees from Iowa State University, all in Applied Mathematics.